Process for forming multilayer wiring
US5498768A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 1993 |
| Grant date | Mar 12, 1996 |
| Priority date | — |
| Expiry date | Jul 6, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/906
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
The present invention relates to a method for filling small via holes provided to insulating film on a wafer to expose parts of the underlayer of the wafer by metal by means of CVD, and an apparatus therefor. The gist of the present invention lies in that, before CVD is conducted, a surface cleaning treatment of small via hole bottom underlayer surface and a stabilization treatment of insulating film surface activated thereby are carried out successively or simultaneously and optionally an anti-corrosive treatment is applied to underlayer surface, and then the CVD treatment is conducted without exposing the underlayer metal subjected to above treatments to the air. The present invention provides an effect of enabling via filling by metal which shows good selectivity and gives a low interfacial resistance between underlayer metal and filled metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.