Method of fabricating an asymmetric lightly doped drain transistor device
US5510279A · kind A · utility
56Cited by
6References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 6, 1995 |
| Grant date | Apr 23, 1996 |
| Priority date | — |
| Expiry date | Jan 6, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26586
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating an asymmetric lightly doped drain transistor device. The device's drain region is shielded with a barrier layer when ion implantation is applied to a implant a highly doped source region. A large angle implantation then follows to form a lightly doped pocket region adjacent to the highly doped source region. The implantation forming the pocket region increases the doping concentration along the device's source side which increases the device's threshold voltage diminishing short channel effects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.