Method of forming a transistor
US5516710A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 1994 |
| Grant date | May 14, 1996 |
| Priority date | — |
| Expiry date | Nov 10, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming a transistor for a bipolar, CMOS, or bipolar CMOS integrated circuit. The method is applicable to forming a double polysilicon self-aligned bipolar transistor using a single masking step for defining the emitter structure with a narrow emitter-base contact area and a large emitter contact area. The method comprises selectively providing a tapered body of dielectric to mask a region of the substrate on which an emitter is to be formed. A conductive layer is provided around the tapered body to form base contact electrodes. The tapered body is selectively removed from the substrate without damaging the underlying silicon substrate, to leave a tapered opening; localized dielectric isolation is provided in the form of sidewall spacers on the first conductive layer. The tapered opening is filled with a layer of a second conductive material to form a second electrode i.e. an emitter structure. The resulting structure is fully planarized, preferably by chemical mechanical polishing, to form coplanar contact areas to the base and emitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.