BIST tester for multiple memories
US5535164A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1995 |
| Grant date | Jul 9, 1996 |
| Priority date | — |
| Expiry date | Mar 3, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention, provides a single BIST which can test various memories of different sizes, types and characteristics by using a state machine to select and generate all patterns required for testing all of the memories on the chip, and impressing all of the data, including expected data, and address information on all of the memories simultaneously. The BIST also generates unique (separate) control signals for the various memories and impresses these control signals on the various memories. The BIST selectively asserts the various control signals so as to apply (write) the data and to read and capture (load result) failure information only to/from those memories whose unique controls are asserted. Selective assertion of a memory's write enable signal prevents multiple writes to a location which can potentially mask cell write and leakage defects while selective assertion of a memory's load result signal is performed only when valid memory output data is expected so as not to capture false error information. The control signals instruct those memories that do not use a particular sequence of inputs or any portion of a given sequence of inputs to "ignore" such signals, thereby…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.