Method for interconnecting semiconductor devices
US5536683A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 1995 |
| Grant date | Jul 16, 1996 |
| Priority date | — |
| Expiry date | Jun 15, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76895
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an interconnect structure within a semiconductor device. An isolation region which defines an active region is formed upon a semiconductor substrate. A gate electrode is formed upon the active region and an interconnect is formed partially upon the active region and partially upon the isolation region. A low dose ion implant is then provided into the active region not covered by the gate or the interconnect. A pair of insulator spacers are then formed at opposite edges of the gate. A source/drain electrode is then formed within the active region between the gate electrode and the interconnect, and a second source/drain electrode is formed within the active region between the isolation region and the gate. Finally, a metal silicide layer is formed bridging adjoining surfaces of the interconnect and the first source/drain electrode. In a second embodiment, the source/drain electrodes are formed after the metal silicide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.