Non-random sub-lithography vertical stack capacitor

US5538592A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Bomy Chen · Cupertino, US
• Gary B. Bronner · Stormville, US
• Son V. Nguyen · Irvine, US

Key dates

• Filing date: Jul 22, 1994
• Grant date: Jul 23, 1996
• Expiry date: Jul 22, 2014

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/947

Abstract

Integrated circuit structures of sub-lithography dimensions are formed by conformal deposition of alternating layers of materials having differing etch rates within an aperture over a body of material to be etched. One of the materials in the alternating layers is then selectively and preferentially etched to form a mask through which etching can be performed on the body of material to be etched. This technique is particularly suited to the formation of structurally robust capacitors for memory cells which have greatly increased plate area, resulting in increased capacitance, while maintaining a small footprint for the capacitor structure.