Semiconductor manufacturing process for low dislocation defects
US5562770A · kind A · utility
18Cited by
12References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 22, 1994 |
| Grant date | Oct 8, 1996 |
| Priority date | — |
| Expiry date | Nov 22, 2014 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/938
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
The present invention provides a method of global stress modification which results in reducing number of dislocations in an epitaxially grown semiconducting device layer on a semiconductor substrate where the device layer and the substrate have a lattice mismatch. The invention teaches a method of imparting a convex curvature to the substrate by removing layer(s) of thin film from or adding layers of thin film to the back side of the substrate, so as to achieve a reduced dislocation density in the device layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.