Method of fabricating self-aligned contact trench DMOS transistors
US5567634A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 1995 |
| Grant date | Oct 22, 1996 |
| Priority date | — |
| Expiry date | May 1, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
A method of fabricating a trench DMOS transistor structure results in the contact to the transistor's source and body being self-aligned to the trench. With a self-aligned contact, the distance from the edge of the source and body contact to the edge of the trench can be minimized. Thus, the distance between the trench edges can be reduced. As a result, the packing density of the transistor is increased dramatically. This gives rise to much improved performance in terms of low on-resistance and higher current drive capability. The process flow maximizes the height of the trench poly gate prior to formation of oxide spacers for the self-contact contact, thereby ensuring sufficient step height for the spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.