Semiconductor integrated circuit device including a memory device having memory cells with increased information storage capacitance
US5578849A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Nov 16, 1994 |
| Grant date | Nov 26, 1996 |
| Priority date | — |
| Expiry date | Nov 16, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
A memory device has a semiconductor substrate, and memory cells provided at intersections between word line conductors and bit line conductors. Each memory cell has a switching transistor and an information storage capacitor. Adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which first semiconductor regions of the transistors of the adjacent two memory cells are united at their boundary into a single region and are connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the transistors of the adjacent two memory cells are connected to word line conductors adjacent to each other, respectively, the second semiconductor regions of the transistors of the adjacent two memory cells are connected to the respective information storage capacitors. A series of memory cell pair unit structures formed under one bit line conductor is positionally shifted with respect to a series of memory cell pair unit structures formed under adjacent first and second bit line conductors on opposite sides of the one bit line conductor, respectively, such that a second information storage capacitor of a memory cell p…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.