CMOS EEPROM cell with tunneling window in the read path
US5587945A · kind A · utility
98Cited by
10References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1995 |
| Grant date | Dec 24, 1996 |
| Priority date | — |
| Expiry date | Nov 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CMOS memory cell including PMOS and NMOS transistors with a common floating gate. The CMOS memory cell includes a first capacitor connecting a first control voltage to the common floating gate and a second tunneling capacitor connected from the common floating gate to the source of the NMOS transistor. The tunneling capacitor includes a tunneling oxide region utilized to charge or discharge the floating gate during program or erase. The CMOS cell further includes a pass transistor with a source to drain path connecting the source of the NMOS transistor to a second control voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.