Flash EEPROM array with floating substrate erase operation
US5598369A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Jan 28, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash EEPROM cell array is erased by applying a relatively high positive voltage to the source region of the cell and a ground potential to the control gate of the cell while allowing the voltage of the drain region and the substrate region of the cell to float. By floating the substrate, the source current during erase is greatly reduced since the only DC current path is between the control gate and the source region. Since the source current is small, a double-diffused junction is not required so that the cell can occupy a minimum area for a given design rule and the cell fabrication process is simplified. In addition, the generation of high energy holes is suppressed and improved performance may be obtained. Because the source current is small during the erase operation, the high positive voltage at the source region can be generated by an on chip charge pump from a supply voltage as low as +3 V. This simplifies the design of memory boards on which many flash EEPROM chips are to be placed. Moreover, the after erase Vt distribution of the memory cell is tightened since a relatively high positive voltage is applied to the source region during erasure. Finally, there is no issue …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.