Wafer transport method
US5601686A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 1996 |
| Grant date | Feb 11, 1997 |
| Priority date | — |
| Expiry date | May 3, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/935
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer transport method including the steps of preparing a semiconductor process equipment having a transport chamber, a process chamber, an interface means for connecting the transport chamber to the process chamber, and a transport means for transporting a semiconductor wafer from the transport chamber to the process chamber by way of the interface means; inserting the transport means mounting a substrate in a communicating corridor including a supply means and an exhaust means; and transporting the substrate while performing the supply and exhaust by sequentially controlling a supply shutoff means, an exhaust shutoff means, and a communicating shutoff means according to the position of a conductance part formed of a gap between the transport means and the communicating corridor. With this method, the substrate is transported at a high throughput without the contamination on the substrate while keeping the different atmospheric conditions of the transport chamber and the process chamber, thereby manufacturing a semiconductor device with a high performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.