Electrically erasable and programmable non-volatile and multi-level memory systemn with write-verify controller
US5602789A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 1995 |
| Grant date | Feb 11, 1997 |
| Priority date | — |
| Expiry date | Aug 22, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An EEPROM for storing multi-level data includes a memory cell array in which electrically erasable and programmable memory cells are arranged in matrix and each of the memory cells has at least three storage states, a write circuit for writing data to the memory cells, first and second write verify means each constituted of a sense amplifier, a data latch circuit and a detection circuit, for verifying an insufficient-written state of a memory cell and an excess-written state of a memory cell, respectively, an additional write circuit for additionally writing data to the memory cell in the insufficient-written state, and an additional erase circuit for additionally erasing data from the memory cell in the excess-written state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.