MOS transistor having adjusted threshold voltage formed along with other transistors

US5618743A · kind A · utility

Assignee

• SILICONIX INCORPORATED · US

Inventors

• Richard K. Williams · Cupertino, US
• Hamza Yilmaz · Saratoga, US
• Michael E. Cornell · Campbell, US
• Jun-Wei Chen · Tianjin, CN

Key dates

• Filing date: Jun 5, 1995
• Grant date: Apr 8, 1997
• Expiry date: Jun 5, 2015

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/983

Abstract

A process is disclosed (hereafter referred to as the "BiCDMOS Process") which simultaneously forms bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes, and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.