Method for improving the manufacturability of the spin-on glass etchback process
US5618757A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 1996 |
| Grant date | Apr 8, 1997 |
| Priority date | — |
| Expiry date | Jan 30, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/941
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Spin-on glass etchback is a technique commonly used to planarize the surface of a semiconductor wafer during fabrication. The etch rate of spin-on glass is largely affected by the amount of oxide exposed during the spin-on glass etchback process. The amount of oxide exposed during spin-on glass etchback is dependent upon the underlying pattern density of topography. A method of standardizing the pattern density of topography for different layers of semiconductor wafers to improve the spin-on glass etchback process used to planarize the surface of a wafer during processing is disclosed. In order to achieve a standardized pattern density of topography on the surface of a wafer, dummy raised areas are added into gaps between active conductive traces on a trace layer. In some embodiments, the standardized pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised areas are formed from a metallic material that is deposited in one single step with an oxide layer deposited over both the active conductive traces and the dummy raised areas prior to the application of spin-on glass and the spin-on glass etchback p…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.