Method and apparatus for making integrated circuits by inserting buffers into a netlist to control clock skew
US5638291A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1994 |
| Grant date | Jun 10, 1997 |
| Priority date | — |
| Expiry date | Oct 14, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/396
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees. The invention includes developing a set of circuit specifications including maximum clock skew, minimum driveability, and maximum ramp delay. These specifications are described in a hardware description language on a digital computer system, and a netlist is synthesized from this hardware description. A modified netlist is then formed by analyzing the netlist and inserting buffers into it to satisfy the circuit specifications of skew, driveabilility, and ramp delay. Thereafter, a digital integrated circuit is produced as specified by the modified netlist.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.