Self-aligned implant energy modulation for shallow source drain extension formation
US5650343A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Jul 22, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for forming shallow and/or lightly doped regions of impurity concentration adjacent to source/drain semiconductor regions in a semiconductor device. In one embodiment, the invention comprises: (a) providing a semiconductor of a first conductivity type having a first surface; (b) forming a gate structure on said first surface, the gate structure including a gate oxide layer and a polysilicon layer, and a ledge; and (c) implanting an impurity of a second conductivity type into the material and the ledge whereby a portion of the implant enters the substrate after passing through the ledge area overlying the edge of the gate and enters the substrate to a first depth below the surface, while a second portion of the implant does not pass through the ledge and enters the substrate to a depth below the surface of the substrate deeper than the first portion. In addition, an apparatus is disclosed, The apparatus may include a substrate having a surface; an insulating layer on the surface of the substrate, having a surface; a gate material layer on the surface of the insulating layer, the gate material layer having a surface; and an overhanging ledge comprised of an etchable materia…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.