Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor
US5657472A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1995 |
| Grant date | Aug 12, 1997 |
| Priority date | — |
| Expiry date | Mar 31, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface for sending memory transaction requests to the system controller and for receiving cache access requests from the system controller corresponding to memory transaction requests by other ones of the data processors. In the preferred embodiment, each memory transaction request is classified into one of two distinct master classes: a first transaction class including read memory access requests and a second transaction class including writeback memory access requests. The master interface and system controller have corresponding parallel request queues, one for …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.