Unbalanced latch and fuse circuit including the same
US5659498A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 1996 |
| Grant date | Aug 19, 1997 |
| Priority date | — |
| Expiry date | Jul 19, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A latch circuit that is intentionally unbalanced, so that a first output reaches ground voltage and a second output reaches a supply voltage. The latch circuit may be used with a fully static low-consumption fuse circuit which reverses the first and second outputs of the latch circuit when the fuse is in an unprogrammed state, but does not change the outputs of the latch circuit in the programmed state. In particular, the latch circuit has a first transistor of a first polarity series connected at a first output node with a second transistor of a second polarity between a supply voltage and a ground voltage. A third transistor of the first polarity is series connected at a second output node with a fourth transistor of the second polarity between the supply voltage and the ground voltage. The gate terminals of the first and second transistors are connected to the second output, while the gate terminals of the third and fourth transistors are connected to the first output. The first and third transistors have thresholds which are mutually different, and the second and fourth transistors have thresholds which are mutually different, so that the first output reaches ground voltage and…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.