Method for forming concurrent top oxides using reoxidized silicon in an EPROM

US5665620A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Bich-Yen Nguyen · Austin, US
• Sergio A. Ajuria · Austin, US
• Wayne M. Paulson · Chandler, US
• Jon Dahm · Austin, US

Key dates

• Filing date: Aug 1, 1994
• Grant date: Sep 9, 1997
• Expiry date: Aug 1, 2014

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A stack of oxide (16) and silicon nitride (18) is grown/deposited over a patterned polysilicon line, which typically acts as a bottom capacitor plate. A thin layer of amorphous or polycrystalline silicon (20) is deposited over the blanket silicon nitride film. The thickness of the deposited silicon layer must be optimized according to the final amount of oxide desired over the silicon nitride, which will be roughly twice the thickness of the deposited silicon film. The oxide/nitride/silicon stack is then patterned and etched, stopping either at or underneath the bottom oxide. Any subsequent cleaning in potentially oxide-etching chemistries (including HF) is done with the protective silicon deposit on top of the silicon nitride. The entire structure is then thermally oxidized, transforming the deposited silicon into silicon oxide (30). Where the structure has been cleared down to the substrate by etching, a second gate oxide is simultaneously formed.