Selective electroless copper deposited interconnect plugs for ULSI applications
US5674787A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 1996 |
| Grant date | Oct 7, 1997 |
| Priority date | — |
| Expiry date | Jan 16, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/81
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method or utilizing electroless copper deposition to selectively form encapsulated copper plugs to connect conductive regions on a semiconductor. A via opening in an inter-level dielectric (ILD) provides a path for connecting two conductive regions separated by the ILD. Once the underlying metal layer is exposed by the via opening, a SiN or SiON dielectric encapsulation layer is formed along the sidewalls of the via. Then, a contact displacement technique is used to form a thin activation layer of copper on a barrier metal, such as TiN, which is present as a covering layer on the underlying metal layer. After the contact displacement of copper on the barrier layer at the bottom of the via, an electroless copper deposition technique is then used to auto-catalytically deposit copper in the via. The electroless copper deposition continues until the via is almost filled, but leaving sufficient room at the top in order to form an upper encapsulation layer. The SiN or SiON sidewalls, the bottom barrier layer and the cap barrier layer function to fully encapsulate the copper plug in the via. The plug is then annealed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.