Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system
US5684977A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1995 |
| Grant date | Nov 4, 1997 |
| Priority date | — |
| Expiry date | Mar 31, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0822
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface for sending memory transaction requests to the system controller. The system controller processes each memory transaction and maintains a set of duplicate cache tags (Dtags) for each data processor. Finally, the system controller contains transaction execution circuitry for activating a transaction for servicing by the interconnect. The transaction execution circuitry pipelines memory access requests from the data processors, and includes invalidation circuitry for processing each writeback request from a given data processor prior to activation to determine if the Dtag index corresponding to the victimized cache line …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.