Shared L2 support for inclusion property in split L1 data and instruction caches
US5694573A · kind A · utility
23Cited by
16References
2Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 30, 1996 |
| Grant date | Dec 2, 1997 |
| Priority date | — |
| Expiry date | Dec 30, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-processor data processing system has a multi-level cache wherein each processor has a split high level (e.g., level one or L1) cache composed of a data cache (DCache) and an instruction cache (ICache). A shared lower level (e.g., level two or L2) cache includes a cache array which is a superset of the cache lines in all L1 caches. There is a directory of L2 cache lines such that each line has a set of inclusion bits indicating if the line is residing in any of the L1 caches. A directory management system requires only N+2 inclusion bits per L2 line, where N is the number of processors having L1 caches sharing the L2 cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.