Method of utilizing redundancy testing to substitute for main array programming and AC speed reads
US5724365A · kind A · utility
8Cited by
5References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 1996 |
| Grant date | Mar 3, 1998 |
| Priority date | — |
| Expiry date | May 24, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of testing Flash memory devices by performing wafer sort testing on main array cells and redundancy array cells of the Flash memory device and performing class testing on redundancy array cells only. There is a major savings of testing time with no decrease in quality of the final product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.