Method and circuit for rapidly equilibrating paired digit lines of a memory device during testing
US5732033A · kind A · utility
29Cited by
9References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 1996 |
| Grant date | Mar 24, 1998 |
| Priority date | — |
| Expiry date | Nov 14, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for rapidly equilibrating paired digit lines of the memory array of a dynamic random access memory device during testing of the memory device includes a plurality of pass gates which are used to connect the equilibrating voltage directly to the paired digit lines, bypassing the conventional equilibration circuitry of the memory device. The pass gates used are contained in spare rows of the memory array and are fabricated as part of the memory device. The pass gates are enabled by activating the row lines for the spare rows while the memory device is being operated in a test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.