Single piece package for semiconductor die
US5739585A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1996 |
| Grant date | Apr 14, 1998 |
| Priority date | — |
| Expiry date | Jul 29, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49133
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for packaging a bare semiconductor die using a one piece package body with a pattern of external conductors is provided. The package body includes a die mounting location and an interconnect opening that aligns with the bond pads on the die. Electrical interconnects, such as wire bonds, are formed through the interconnect opening to establish electrical communication between the bond pads on the die and the conductors on the package body. The conductors on the package body can include solder bumps to permit the package to be flip chip mounted to a supporting substrate such as a printed circuit board or to be mounted in a chip-on-board configuration. The package can be fabricated by bulk micro-machining silicon wafers to form the package bodies, attaching the dice to the package bodies, and then singulating the wafer. Alternately the package body can be formed of a FR-4 material. In addition, multiple dice can be attached to a package body to form a multi-chip module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.