Process having high tolerance to buried contact mask misalignment by using a PSG spacer
US5742088A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 1997 |
| Grant date | Apr 21, 1998 |
| Priority date | — |
| Expiry date | Apr 18, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/743
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A new method of forming improved buried contact junctions is described. A layer of polysilicon overlying gate silicon oxide is provided over the surface of a semiconductor substrate and etched away to provide an opening to the substrate where a planned buried contact junction will be formed. A second doped polysilicon layer and a tungsten silicide layer are deposited and patterned to provide gate electrodes and a contact overlying the planned buried contact junction and providing an opening to the substrate where a planned source/drain region will be formed adjoining the planned buried contact junction and wherein a portion of the polysilicon layer not at the polysilicon contact remains as residue. The residue is etched away whereby a trench is etched into the substrate at the junction of the planned source/drain region and the planned buried contact junction. A doped glasseous layer is deposited overlying the patterned tungsten silicide/polysilicon layer and within the trench, then isotropically etched away until it remains only partially filling the trench. The substrate is oxidized to drive-in dopant from the doped glasseous layer within the trench into the surrounding substrate…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.