Fluted via formation for superior metal step coverage
US5746884A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 1996 |
| Grant date | May 5, 1998 |
| Priority date | — |
| Expiry date | Aug 13, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a via in a interlevel dielectric of a semiconductor device wherein the via has a fluted sidewall. A semiconductor substrate is provided having a first conductive layer formed thereon. A dielectric layer is then formed on the first conductive layer. A photoresist layer is deposited on a dielectric layer and a contact opening is formed in the photoresist layer to expose a contact region of the dielectric layer. A first etch step is performed to remove portions of the dielectric layer proximal to the contact region to form a first stage of the fluted via. The first stage includes a first sidewall stage extending from an upper surface of the dielectric layer at an angle less than 50.degree.. The first stage of the fluted via extends a first lateral distance which is greater than a lateral dimension of the contact opening. A second etch step is then performed to further remove portions of the dielectric layer to form a second stage of the fluted via. The second stage includes a second sidewall stage extending from the first sidewall stage at a second angle between 40.degree. and 70.degree.. A third etch step is then performed to further remove portions of the dielect…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.