Reference word line and data propagation reproduction circuit for memories provided with hierarchical decoders
US5754483A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 1997 |
| Grant date | May 19, 1998 |
| Priority date | — |
| Expiry date | Mar 27, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reference word line and data propagation reproduction circuit, particularly for non-volatile memories provided with hierarchical decoders, where the memory is divided into at least two memory half-matrices that are arranged on different half-planes. The circuit includes, for each one of the at least two memory half-matrices, a reference unit for each one of the at least two memory half-matrices and an associated unit for reproducing the propagation of the signals along the reference unit. The reference unit and the associated propagation reproduction unit have a structure that is identical to each generic word line of the memory device. The reference and propagation reproduction units of one of the at least two memory half-matrices are activatable upon selection of a memory cell in the other one of the at least two memory half-matrices, in order to provide a reference that is synchronous and symmetrical with respect to the selection of the memory cell for reading it and so as to preset, according to the propagation reproduction unit conditions for starting correct and certain reading of the selected memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.