Semiconductor package
US5786632A · kind A · utility
20Cited by
18References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1996 |
| Grant date | Jul 28, 1998 |
| Priority date | — |
| Expiry date | Sep 24, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for packaging a semiconductor die includes forming an additional protective layer and conductive traces on the die. The die is then placed in a multi-die holder having electrical connectors for establishing an electrical connection to the conductive traces. The protective layer is formed as a thin or thick film of an electrically insulating material such as a polymer, glass, nitride or oxide. In addition, the protective layer can be formed with a tapered peripheral edge to facilitate insertion of the die into the die holder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.