Memory device using a reduced word line voltage during read operations and a method of accessing such a memory device
US5796651A · kind A · utility
14Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 19, 1997 |
| Grant date | Aug 18, 1998 |
| Priority date | — |
| Expiry date | May 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device uses a reduced word line voltage during READ operations. The memory device includes a memory cell and a pass transistor for accessing the cell. The cell includes a storage node coupled to a pull-down transistor having substantially the same conductivity as the pass transistor. A drive circuit generates a reduced word line voltage to activate the pass transistor during a READ operation. The reduced word line voltage has a magnitude less than the magnitude of the bias voltage used to activate the pull-down transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.