Zero consumption power-on-reset
US5821788A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 1997 |
| Grant date | Oct 13, 1998 |
| Priority date | — |
| Expiry date | Jan 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/143
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power-on-reset (P.O.R.) circuit produces a power-on-reset (P.O.R.) signal whose an amplitude tracks the voltage on a supply node until it exceeds a certain threshold. The circuit has a first monitoring and comparing circuit portion including at least a nonvolatile memory element having a control gate coupled to the supply node, a first current terminal coupled to a ground node, and a second current terminal coupled to a first node which is capacitively coupled to the supply node. The circuit further includes a second circuit portion that includes an intrinsically unbalanced bistable circuit, having a node that intrinsically is in a high state at power-on coupled to the first node that is intrinsically in a low state at power-on coupled to the input of an output buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.