Protected encapsulation of catalytic layer for electroless copper interconnect
US5824599A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jan 16, 1996 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Jan 16, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/89
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for utilizing electroless copper deposition to form interconnects on a semiconductor. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is deposited. Then, a catalytic copper seed layer is conformally blanket deposited in vacuum over the barrier layer. Next, without breaking the vacuum, an aluminum protective layer is deposited onto the catalytic layer to encapsulate and protect the catalytic layer from oxidizing. An electroless deposition technique is then used to auto-catalytically deposit copper on the catalytic layer. The electroless deposition solution dissolves the overlying protective layer to expose the surface of the underlying catalytic layer. The electroless copper deposition occurs on this catalytic surface, and continues until the via/trench is filled. Subsequently, the copper and barrier material are polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in ord…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.