Single-core two-side substrate with u-strip and co-planar signal traces, and power and ground planes through split-wrap-around (SWA) or split-via-connections (SVC) for packaging IC devices
US5825084A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 1997 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Feb 11, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15747
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a new substrate with two metal layer circuit structure and layout for semiconductor packaging. The speed and performance characteristics of the semiconductor device are optimized while the packaging structure is simplified by utilizing only one dielectric layer and conventional printed circuit board fabrication process. The difficulties encountered due to the complexities and higher cost of production required for the multiple layer and high density configuration are thus avoided. The improved circuit structure is achieved by implementing a segmented ring on one side of a substrate and a split plane on the other side thus forming a single layer substrate structure. The edges of the substrate are coated with metal layer to provide inter-layer connections. In addition to the benefits of high performance, low cost, the improved circuit structure and package layout provide flexibility allowing higher degree of freedom for selecting the location and number of input and output signal lines and connections to the ground and power planes from the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.