Method of making high resistive structures in salicided process semiconductor devices
US5834356A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 1997 |
| Grant date | Nov 10, 1998 |
| Priority date | — |
| Expiry date | Jun 27, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/47
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for making a high resistive structure in a salicided process. The method includes providing a substrate including at least one active device having diffusion regions and a polysilicon gate structure. Depositing a metallization layer over the substrate including at least one active device. Annealing the substrate to cause at least part of metallization layer to form a metallization silicided layer over the substrate that includes the at least one active device. Preferably, the metallization silicided layer lying over the diffusion regions and the polysilicon gate produces a substantially decreased level of sheet resistance. The method also includes forming a mask over the metallization silicided layer, and the mask being configured to leave a portion of the metallization silicided layer that overlies at least one active device exposed. Further, the method includes etching the substrate in order to remove the exposed metallization silicided layer overlying the at least one active device to produce a substantially increased level of sheet resistance over the at least one active device not having the metallization silicided layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.