Hierarchic memory device having auxiliary lines connected to word lines
US5841728A · kind A · utility
1Cited by
7References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1996 |
| Grant date | Nov 24, 1998 |
| Priority date | — |
| Expiry date | Sep 30, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory device in accordance with the present invention has hierarchical row decoding architecture and comprises at least one main decoder and a plurality of secondary decoders. The decoders have outputs coupled to a plurality of word lines respectively through a plurality of auxiliary lines having first ends respectively connected to said outputs and second ends respectively connected to intermediate points of the word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.