Memory cell having increased capacitance via a local interconnect to gate capacitor and a method for making such a cell
US5844836A · kind A · utility
12Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 24, 1997 |
| Grant date | Dec 1, 1998 |
| Priority date | — |
| Expiry date | Mar 24, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure. The capacitive structure includes a dielectric material between polysilicon conductive lines and tungsten local interconnects. The polysilicon plates are each connected to drains of lateral transistors associated with the SRAM cell. A dielectric material such as silicon dioxide may be deposited between the local interconnect and polysilicon conductive lines. The capacitor structures are provided between first and second N-channel pull down transistors associated with the SRAM cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.