Method and apparatus for writing to memory components
US5844855A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 1997 |
| Grant date | Dec 1, 1998 |
| Priority date | — |
| Expiry date | May 16, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction w…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.