Method for etching transistor gates using a hardmask

US5851926A · kind A · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Ajay Kumar · Fairport, US
• Jeffrey D. Chinn · Foster City, US
• Shashank Deshmukh · San Jose, US
• Weinan Jiang · Nanhu, CN
• Rolf Guenther · Monte Sereno, US
• Bruce Minaee · Napa, US
• Mark Wiltse · Taipei, TW

Key dates

• Filing date: Oct 1, 1996
• Grant date: Dec 22, 1998
• Expiry date: Oct 1, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/32135
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An etchant composition of nitrogen trifluoride and chlorine, preferably also including a passivation material such as hydrogen bromide, etches tungsten silicide-polysilicon gate layers with high selectivity to a thin underlying silicon oxide gate oxide layer to form straight wall, perpendicular profiles with low microloading and excellent profile control.