Method of stress testing memory integrated circuits
US5852581A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 1996 |
| Grant date | Dec 22, 1998 |
| Priority date | — |
| Expiry date | Jun 13, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/56
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory self-stress mode capable of use during wafer burn-in such as for dynamic random access memory (DRAM) integrated circuits. A burn-in power supply voltage and ground voltage delivered to a common node of a plurality of memory cell storage capacitors and to an equilibrate node coupled to bit lines. An all row high test cycles word lines between a binary low logic level and a binary high logic level, thereby stressing the dielectric of the memory cell storage capacitors by imposing stress voltages of differing polarity. A half row high test cycles alternate word lines of a word line sequence thereby stressing undesired short circuit connections between adjacent word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.