Creation of a self-aligned, ion implanted channel region, after source and drain formation
US5856225A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 1997 |
| Grant date | Jan 5, 1999 |
| Priority date | — |
| Expiry date | Nov 24, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28052
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a MOSFET device, in which a source and drain region has been formed, prior to the formation of an ion implanted channel region, has been developed. The early creation of source and drain region allows a high temperature anneal to be performed, removing damage resulting from the source and drain ion implantation procedures, however without redistribution of channel dopants. The method features creating an opening in an insulator layer, after the source and drain formation, and then forming the channel region in the semiconductor substrate, directly underlying the opening in the insulator layer. A polysilicon gate structure is next formed in the opening, resulting in self-alignment to the underlying channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.