Semiconductor package and method for fabricating the same
US5858815A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Dec 11, 1996 |
| Grant date | Jan 12, 1999 |
| Priority date | — |
| Expiry date | Dec 11, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for manufacturing chip size semiconductor package with a light, thin, and compact structure having a reduced size of its semiconductor chip while having an increased number of pins For the package, it is possible to use either the semiconductor chip having bond pads arranged on end portions of the chip or the semiconductor chip having bond pads arranged on the central portion of the chip. In either case, input/output terminals of the package are arranged in the form of an area array. Accordingly, when the package is mounted on an electronic appliance, its mounting area can be minimized, thereby achieving a compactness of the final product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.