Semiconductor integrated circuit device having capacitance element and process of manufacturing the same
US5880497A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 1996 |
| Grant date | Mar 9, 1999 |
| Priority date | — |
| Expiry date | Jan 26, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/904
Abstract
A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.