Constraint driven insertion of scan logic for implementing design for test within an integrated circuit design
US5903466A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1995 |
| Grant date | May 11, 1999 |
| Priority date | — |
| Expiry date | Dec 29, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A computer implemented process and system for providing a scan insertion process having a reduced set of constraint driven compiler optimizations that provide an efficient and effective optimization for design for test implementations. The present invention includes a three tiered effort performance optimization process within a scan insertion process; a first tier operates to perform a set of optimizations (size design) only on elements of the design added for design for test (DFT). The second tier offers the first tier and performs the size design optimizations across all of the design while the third tier offers the second tier with sequential optimizations, circuit size downs, and another size design. Each higher user-selectable tier offers more complex optimizations and consumes additional processing time. An option to perform design constraints optimization (max fanout, max signal transition, and max capacitance) is also available. By utilizing a reduced set of performance optimizations, the present invention offers a post scan insertion compile technique that is fast enough to be practically used on chip level netlists. Hierarchical compilations for DFT are therefore allowed…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.