Method of manufacture of single transistor ferroelectric memory cell using chemical-mechanical polishing

US5907762A · kind A · utility

Assignees

• Sharp Microelectronics Technology Inc. · US
• SHARP KABUSHIKI KAISHA · JP

Inventors

• David R. Evans · Beaverton, US
• Sheng Teng Hsu · Camas, US
• Jong-Jan Lee · Camas, US

Key dates

• Filing date: Dec 4, 1997
• Grant date: May 25, 1999
• Expiry date: Dec 4, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/701

Abstract

A method of constructing a single-transistor ferroelectric memory (FEM) cell includes: preparing a silicon substrate for construction of a FEM gate unit; forming gate, source and drain regions on the silicon substrate; forming a nitride layer over the structure to a predetermined thickness equal to a specified thickness for a bottom electrode of the FEM gate unit; forming a first insulating layer over the structure; chemically-mechanically polishing the first insulating layer such that the top surface thereof is even with the top of the nitride layer; forming the bottom electrode for the FEM cell; and chemically-mechanically polishing the bottom electrode such that the top surface thereof is even with the top surface of the first insulating layer. Additional layers are formed and polished, depending on the specific final configuration of the FEM cell.