Method of making memory cell with vertical transistor and buried word and body lines

US5909618A · kind A · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Leonard Forbes · Corvallis, US
• Wendell P. Noble · Colchester, US
• Kie Y. Ahn · Chappaqua, US

Key dates

• Filing date: Jul 8, 1997
• Grant date: Jun 1, 1999
• Expiry date: Jul 8, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/395

Abstract

An integrated circuit and fabrication method includes a vertical transistor for a memory cell in a dynamic random access memory (DRAM) or other integrated circuit. Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried gates and body contacts are provided for each access transistor on opposing sides of the pillars. Buried word lines extend in first alternating trenches orthogonal to the bit lines. The buried word lines interconnect ones of the gates. Buried body lines extend in second alternating trenches orthogonal to the bit lines. The buried body lines interconnect body regions of adjacent access transistors. Unitary and split-conductor gate and body lines are provided for shared or independent signals to access transistors on either side of the trenches. In one embodiment, the memory cell has a surface area that is approximately 4 F.sup.2, where F is a minimum feature size. Bulk-semiconductor and semiconductor-on-insulator (SOI) embodiments are provided.