Kie Y. Ahn
615Patents
86h-index
38Co-inventors
90Inventor score
Filing activity: Mar 5, 1975 → Jan 7, 2016
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7045430B2 | Atomic layer-deposited LaAlO3 films for gate dielectrics | Electricity | 670 | Expired |
| US7135421B2 | Atomic layer-deposited hafnium aluminum oxide | Electricity | 632 | Expired |
| US7235501B2 | Lanthanum hafnium oxide dielectrics | Electricity | 628 | Expired |
| US7192824B2 | Lanthanide oxide / hafnium oxide dielectric layers | Electricity | 605 | Expired |
| US7192892B2 | Atomic layer deposited dielectric layers | Electricity | 598 | Expired |
| US7312494B2 | Lanthanide oxide / hafnium oxide dielectric layers | Electricity | 579 | Expired |
| US7405454B2 | Electronic apparatus with deposited dielectric layers | Electricity | 564 | Expired |
| US7393736B2 | Atomic layer deposition of Zrx Hfy Sn1-x-y O2 films as high k gate dielectrics | Electricity | 558 | Expired |
| US7902582B2 | Tantalum lanthanide oxynitride films | Electricity | 505 | Active |
| US6150687A | Memory cell having a vertical transistor with buried source/drain and dual gates | Electricity | 324 | Expired |
| US6570248B1 | Structure and method for a high-performance electronic packaging assembly | Electricity | 310 | Expired |
| US6689660B1 | 4 F2 folded bit line DRAM cell structure having buried bit and word lines | Electricity | 280 | Expired |
| US6514828B2 | Method of fabricating a highly reliable gate oxide | Electricity | 264 | Expired |
| US6072209A | Four F.sup.2 folded bit line DRAM cell structure having buried bit and word lines | Electricity | 256 | Expired |
| US5909618A | Method of making memory cell with vertical transistor and buried word and body lines | Electricity | 241 | Expired |
| US6281042A | Structure and method for a high performance electronic packaging assembly | Electricity | 239 | Expired |
| US6921702B2 | Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics | Emerging Cross-Sectional Technologies | 229 | Expired |
| US6424001B1 | Flash memory with ultra thin vertical body transistors | Electricity | 214 | Expired |
| US6495436B2 | Formation of metal oxide gate dielectric | Electricity | 190 | Expired |
| US6534420B2 | Methods for forming dielectric materials and methods for forming semiconductor devices | Electricity | 189 | Expired |
| US6274937A | Silicon multi-chip module packaging with integrated passive components and method of making | Electricity | 186 | Expired |
| US5981350A | Method for forming high capacitance memory cells | Emerging Cross-Sectional Technologies | 180 | Expired |
| US6514820B2 | Method for forming single electron resistor memory | Emerging Cross-Sectional Technologies | 163 | Expired |
| US6767795B2 | Highly reliable amorphous high-k gate dielectric ZrOXNY | Electricity | 163 | Expired |
| US6778441B2 | Integrated circuit memory device and method | Electricity | 158 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.