Self-test of a memory device
US5910921A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1997 |
| Grant date | Jun 8, 1999 |
| Priority date | — |
| Expiry date | Apr 22, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
DRAM self-test circuitry, when triggered by an external signal, performs an on-chip test of a DRAM memory array. The self-test circuitry writes either all ones or all zeroes to each set of physical rows having the same address within the segment to be tested, and then reads the rows a set at a time. If the data bits comprising the set do not all equal one or zero, a resultant error detection signal is generated and used to latch the failed addresses into a failed address queue. If the data bits are either all zeros or ones, the next set of rows are tested. When the self-test is complete, the failed addresses stored in the queue may be transmitted to an external, off-chip device or analyzed and acted on by on-chip error correction circuitry. The self-test circuitry further includes circuitry to detect data bit transitions between successive failing addresses latched in a the address queue. If the transition circuitry determines that one or more bits have the same logic in all of the failed addresses, a partialing technique may be employed to repair DRAMs that have more failing rows/columns than redundant rows/columns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.