Method for producing deep submicron interconnect vias
US5915203A · kind A · utility
65Cited by
4References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1997 |
| Grant date | Jun 22, 1999 |
| Priority date | — |
| Expiry date | Jun 10, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of producing deep submicron vias is described in which a metal blanket layer is formed on a premetal dielectric and patterned to form line elements. An intermetal dielectric is then deposited over the patterned metal and chemically mechanically polished down to the top of the line elements. A second metal blanket layer is then deposited and patterned to form via studs. An intermetal dielectric is also deposited over the patterned metal via studs and polished down to the tops of the studs. The process is repeated until a multilevel integrated circuit is formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.