Self-aligned silicide gate technology for advanced submicron MOS devices
US5937315A · kind A · utility
31Cited by
9References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 7, 1997 |
| Grant date | Aug 10, 1999 |
| Priority date | — |
| Expiry date | Nov 7, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/668
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A deep submicron MOS device having a self-aligned silicide gate structure and a method for forming the same is provided so as to overcome the problems of poly-Si depletion and boron penetration. A first Nickel silicide layer is formed between a gate oxide and a polycrystalline silicon gate electrode. Further, second Nickel silicide layers are formed over highly-doped source/drain regions. In this fashion, the reliability of the MOS device will be enhanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.